Semiconductor devices are fabricated with surface conductors for the purpose of distributing operating voltages and currents and digital signals between devices. The surface conductors are insulated from the substrate by a layer of dielectric material. If the dielectric layer is made relatively thick, the effects of capacitive coupling will be lessened. On the other hand, it is desirable to recess the dielectric material and keep the surface of the substrate planar. Therefore, trenches or isolations, are etched into the surface of the substrate and filled with dielectric material such as silicon dioxide. One method used to create these isolations is LOCOS (LOCal Oxidation of Silicon). In this process, grooves are etched into the substrate and using a nitride layer as a mask, selected regions of the silicon substrate are oxidized. However, LOCOS cannot meet the requirements of the quarter-micron design. At this small dimension, there are limitations to LOCOS such as bird's beak formation, insulator thinning, non-planarity and stress-induced silicon defects. Insulator thinning contributes to the non-planarity of the device and reduces isolation depth. Bird's beak encroachment degrades conduction at the trench edges (see A. Bryant, et al., Characteristics of CMOS Device Isolation for the ULSI Age, IEDM Technical Digest, P. 671, 1994).
Another method used to create isolations is STI (Shallow Trench Isolation). However, there are limitations with STI as well. When using STI having a vertical trench profile, there are problems with edge conduction, void formation during trench filling, and stress along the trench walls. Edge conduction is more severe the more vertical the trench profile. To reduce this problem, the trench angle should be under 60 degrees. However, this is inadequate for isolation widths below 0.8 .mu.m. To obtain isolation widths below 0.35 .mu.m, the trench angle should be greater than 80 degrees (see K. Ishimaru, et al., Trench Isolation Technology with 1 .mu.m Depth n- and p-wells for A Full-CMOS SRAM Cell with a 0.4 .mu.m n+/p+ Spacing, Symposium on VLSI Technology Digest of Technical Papers, P. 97, 1994). An additional isotropic silicon etch is proposed by Ishimaru to round the trench edges to reduce edge conduction. However, such isotropic silicon etch cannot be easily monitored and controlled. Therefore, device characteristics may be changed from die to die and wafer to wafer.
It is an object of the present invention to provide an improved method for forming shallow trench isolation. Specifically, it is an object of the invention to provide a method for trench edge rounding that is easily monitored and controlled.